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4-MBlT (256K x 16 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
28F400BL-T B 28F004BL-T B
Y
Low Voltage Operation for Very Low-Power Portable Applications VCC e 3 0V - 3 6V Read VCC e 3 15V - 3 6V Program Erase Expanded Temperature Range b 20 C to a 70 C x8 x16 Input Output Architecture 28F400BL-T 28F400BL-B For High Performance and High Integration 16-bit and 32-bit CPUs x8-only Input Output Architecture 28F004BL-T 28F004BL-B For Space Constrained 8-bit Applications Upgradeable to Intel's SmartVoltage Products Optimized High Density Blocked Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks One 96-KB Main Block Three 128-KB Main Blocks Top or Bottom Boot Locations Extended Cycling Capability 10 000 Block Erase Cycles Automated Word Byte Write and Block Erase Command User Interface Status Registers Erase Suspend Capability
Y Y
SRAM-Compatible Write Interface Automatic Power Savings Feature 0 8 mA typical ICC Active Current in Static Operation Very High-Performance Read 150 ns Maximum Access Time 65 ns Maximum Output Enable Time Low Power Consumption 15 mA Typical Active Read Current Reset Deep Power-Down Input 0 2 mA ICC Typical Acts as Reset for Boot Operations Write Protection for Boot Block Hardware Data Protection Feature Erase Write Lockout During Power Transitions Industry Standard Surface Mount Packaging 28F400BL JEDEC ROM Compatible 44-Lead PSOP 56-Lead TSOP 28F004BL 40-Lead TSOP 12V Word Byte Write and Block Erase VPP e 12V g5% Standard ETOX TM III Flash Technology 3 3V Read
Y
Y
Y
Y
Y Y
Y Y
Y
Y
Y
Y
Y
Y
Y
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290450-005
28F400BL-T B 28F004BL-T B
Intel's 4-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure automated write and erase operations and standard microprocessor interface The 4-Mbit Low Power Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input output control very low power very high speed an industry standard ROM compatible pinout and surface mount packaging The 4-Mbit low power flash family opens a new capability for 3V batteryoperated portable systems and is an easy upgrade to Intel's 2-Mbit Low Power Boot Block Flash Memory Family The Intel 28F400BL-T B are 16-bit wide low power flash memory offerings These high density flash memories provide user selectable bus operation for either 8-bit or 16-bit applications The 28F400BL-T and 28F400BL-B are 4 194 304-bit non-volatile memories organized as either 524 288 bytes or 262 144 words of information They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages The x8 x16 pinout conforms to the industry standard ROM EPROM pinout The Intel 28F004BL-T B are 8-bit wide low power flash memories with 4 194 304 bits organized as 524 288 bytes of information They are offered in a 40-Lead TSOP package which is ideal for space-constrained portable systems These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified word byte write and block erasure The 28F400BL-T 28F004BL-T provide block locations compatible with Intel's Low Voltage MCS-186 family i386 TM i486 TM microprocessors The 28F400BL-B 28F004BL-B provide compatibility with Intel's 80960KX and 80960SX families as well as other low voltage embedded microprocessors The boot block includes a data protection feature to protect the boot code in critical applications With a maximum access time of 150 ns these 4-Mbit low power flash devices are very high performance memories at 3 3V which interface to a wide range of low voltage microprocessors and microcontrollers A deep powerdown mode lowers the total VCC power consumption to 0 66 mW which is critical in handheld battery powered systems such as Handy Cellular Phones For very high speed applications using a 5V supply refer to the Intel 28F400BX-T B 28F004BX-T B 4-Mbit Boot Block Flash Memory family datasheet Manufactured on Intel's 0 8 micron ETOX III process the 4-Mbit flash memory family provides world class quality reliability and cost-effectiveness at the 4 Mbit density level
2
28F400BL-T B 28F004BL-T B
10
PRODUCT FAMILY OVERVIEW
1 2 Main Features
The 28F400BL 28F004BL boot block flash memory family is a very high performance 4-Mbit (4 194 304 bit) memory family organized as either 256 KWords (262 144 words) of 16 bits each or 512 Kbytes (524 288 bytes) of 8 bits each Seven Separately Erasable Blocks including a Hardware-Lockable boot block (16 384 Bytes) two parameter blocks (8 192 Bytes each) and four main blocks (1 block of 98 304 Bytes and 3 blocks of 131 072 Bytes) are included on the 4-Mbit family An erase operation erases one of the main blocks in typically 3 4 seconds and the boot or parameter blocks in typically 2 0 seconds independent of the remaining blocks Each block can be independently erased and programmed 10 000 times The Boot Block is located at either the top (-T) or the bottom (-B) of the address map in order to accommodate different microprocessor protocols for boot code location The hardware Iockable boot block provides the most secure code storage The boot block is intended to store the kernel code required for booting-up a system When the RP pin is between 11 4V and 12 6V the boot block is unlocked and program and erase operations can be performed When the RP pin is at or below 4 1V the boot block is locked and program and erase operations to the boot block are ignored The 28F400BL products are available in the ROM EPROM compatible pinout and housed in the 44-Lead PSOP (Plastic Small Outline) package and the 56-Lead TSOP (Thin Small Outline 1 2mm thick) package as shown in Figures 3 and 4 The 28F004BL products are available in the 40-Lead TSOP (1 2mm thick) package as shown in Figure 5 The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the 28F400BL and 28F004BL flash memory products Program and Erase Automation allow program and erase operations to be executed using a twowrite command sequence to the CUI The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations including verifications thereby unburdening the microprocessor or microcontroller Writing of memory data is performed in word or byte increments for the 28F400BL family and in byte increments for the 28F004BL family typically within 11 ms
Throughout this datasheet 28F400BL refers to both the 28F400BL-T and 28F400BL-B devices and 28F004BL refers to both the 28F004BL-T and 28F004BL-B devices The 4-Mbit flash family refers to both the 28F400BL and 28F004BL products This datasheet comprises the specifications for four separate products in the 4-Mbit flash family Section 1 provides an overview of the 4-Mbit flash family including applications pinouts and pin descriptions Sections 2 and 3 describe in detail the specific memory organizations for the 28F400BL and 28F004BL products respectively Section 4 combines a description of the family's principles of operations Finally section 5 describes the family's operating specifications Product Family x8 x16 Products 28F400BL-T 28F400BL-B x8-Only Products 28F004BL-T 28F004BL-B
1 1 Designing for Upgrade to SmartVoltage Products
Today's high volume boot block products are upgradeable to Intel's SmartVoltage boot block products that provide program and erase operation at 5V or 12V VPP and read operation at 3V or 5V VCC Intel's SmartVoltage boot block products provide the following enhancements to the boot block products described in this datasheet 1 DU pin is replaced by WP to provide a means to lock and unlock the boot block with logic signals 2 5V Program Erase operation uses proven program and erase techniques with 5V g10% applied to VPP 3 Enhanced circuits optimize performance at 3 3V VCC Refer to the 2 4 or 8Mbit SmartVoltage Boot Block Flash Memory datasheets for complete specifications When you design with 12V VPP boot block products you should provide the capability in your board design to upgrade to SmartVoltage products Follow these guidelines to ensure compatibility 1 Connect DU (WP on SmartVoltage products) to a control signal or to VCC or GND 2 If adding a switch on VPP for write protection switch to GND for complete write protection 3 Allow for connecting 5V to VPP and disconnect 12V from the VPP line if desired
3
28F400BL-T B 28F004BL-T B
The Status Register (SR) indicates the status of the WSM and whether the WSM successfully completed the desired program or erase operation Maximum Access Time of 150 ns (tACC) is achieved over the commercial temperature range (0 C to a 70 C) VCC supply voltage range (3 0V to 3 6V 4 5V to 5 5V) and 50 pF output load Ipp Program current is 40 mA for x16 operation and 30 mA for x8 operation IPP Erase current is 30 mA maximum VPP erase and programming voltage is 11 4V to 12 6V (VPP e 12V g5%) under all operating conditions Typical ICC Active Current of 15 mA is achieved for the x16 products and the x8 products The 4-Mbit flash family is also designed with an Automatic Power Savings (APS) feature to minimize system battery current drain and allow for very low power designs Once the device is accessed to read the array data APS mode will immediately put the memory in static mode of operation where ICC active current is typically 0 8 mA until the next read is initiated When the CE and RP pins are at VCC and the BYTE pin (28F400BX-L-only) is at either VCC or GND the CMOS Standby mode is enabled where ICC is typically 45 mA A Deep Power-Down Mode is enabled when the PWD pin is at ground minimizing power consumption and providing write protection during power-up conditions ICC current during deep power-down mode is 0 20 mA typical An initial maximum access time or Reset Time of 600 ns is required from RP switching until outputs are valid Equivalently the device has a maximum wake-up time of 1 ms until writes to the Command User Interface are recognized When RP is at ground the WSM is reset the Status Register is cleared and the entire device is protected from being written to This feature prevents data corruption and protects the code stored in the device during system reset The system Reset pin can be tied to RP to reset the memory to normal read mode upon activation of the Reset pin When the CPU enters reset mode it expects to read the contents of a memory location Furthermore with on-chip program erase automation in the 4-Mbit family and the RP functionality for data protection when the CPU is reset and even if a program or erase command is issued the device will not recognize any operation until RP returns to its normal state For the 2SF400BL Byte-wide or Word-wide Input Output Control is possible by controlling the BYTE pin When the BYTE pin is at a logic low the device is in the byte-wide mode (x8) and data is read and written through DQ 0 7 During the bytewide mode DQ 8 14 are tri-stated and DQ15 A b 1 becomes the lowest order address pin When the BYTE pin is at a logic high the device is in the word-wide mode (x16) and data is read and written through DQ 0 15
1 3 Applications
The 4-Mbit low power boot block flash memory family combines high density very low power high performance cost-effective flash memories with blocking and hardware protection capabilities Its flexibility and versatility will reduce costs throughout the product life cycle Flash memory is ideal for Just-In-Time production flow reducing system inventory and costs and eliminating component handling during the production phase During the product life cycle when code updates or feature enhancements become necessary flash memory will reduce the update costs by allowing either a user-performed code change via floppy disk or a remote code change via a serial link The 4-Mbit flash family provides full function blocked flash memories suitable for a wide range of applications These applications include Extended PC BIOS and ROM-able applications storage Handy Digital Cellular Phone program and data storage and various other low power embedded applications where both program and data storage are required Portable systems such as Notebook Palmtop computers are ideal applications for the 4-Mbit low power flash products Portable and handheld personal computer applications are becoming more complex with the addition of power management software to take advantage of the latest microprocessor technology the availability of ROM-based application software pen tablet code for electronic hand writing and diagnostic code Figure 1 shows an example of a 28F400BL-T application This increase in software sophistication augments the probability that a code update will be required after the Notebook is shipped The 4-Mbit flash products provide an inexpensive update solution for the notebook and handheld personal computers while extending their product lifetime Furthermore the 4-Mbit flash products' deep power-down mode provides added flexibility for these battery-operated portable designs which require operation at very low power levels
4
28F400BL-T B 28F004BL-T B
The 4-Mbit low power flash products also provide excellent design solutions for Handy Digital Cellular Phone applications requiring low voltage supply high performance high density storage capability coupled with modular software designs and a small form factor package (x8-only bus) The 4-Mbit's blocking scheme allows for an easy segmentation of the embedded code with 16-Kbytes of HardwareProtected Boot code 4 Main Blocks of program code and 2 Parameter Blocks of 8-Kbytes each for frequently updatable data storage and diagnostic messages (e g phone numbers authorization codes) Figure 2 is an example of such an application with the 28F004BL-T These are a few actual examples of the wide range of applications for the 4-Mbit low power Boot Block flash memory family which enable system designers achieve the best possible product design Only your imagination limits the applicability of such a versatile low power product family
290450 - 7
Figure 1 28F400BL Interface to Intel386 TM EX Embedded Processor
290450 - 23
Figure 2 28F004BL Interface to INTEL 80L188EB Low Voltage 8-bit Embedded Processor
5
28F400BL-T B 28F004BL-T B
pinout shown in Figure 4 provides density upgrades to future higher density boot block memories The 28F004BL 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density upgrade for the 28F002BL 2-Mbit Low Power Boot Block flash memory family
1 4 Pinouts
The 28F400BL 44-Lead PSOP pinout follows the industry standard ROM EPROM pinout as shown in Figure 3 and provides an upgrade for the 28F200BL Low Power Boot Block flash memory family Furthermore the 28F400BL 56-Lead TSOP
290450 - 24
Figure 3 PSOP Lead Configuration for x8 x16 28F400BL
6
28F400BL-T B 28F004BL-T B
290450 - 6
Figure 4 TSOP Lead Configuration for x8 28F400BL
290450 - 5
Figure 5 TSOP Lead Configuration for x8 28F004BL 7
28F400BL-T B 28F004BL-T B
1 5 Pin Descriptions for x8 x16 28F400BL
Symbol A0 -A17 A9 Type I I Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle ADDRESS INPUT When A9 is at 12V the signature mode is accessed During this mode A0 decodes between the manufacturer and device ID's When BYTE is at a logic low only the lower byte of the signatures are read DQ15 Ab1 is a don't care in the signature mode when BYTE is low DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle during a program command Inputs commands to the command user interface when CE and WE are active Data is internally latched during the write and program cycles Outputs array Intelligent Identifier and status register data The data pins float to tri-state when the chip is deselected or the outputs are disabled DATA INPUT OUTPUTS Inputs array data on the second CE and WE cycle during a program command Data is internally latched during the write and program cycles The data pins float to tri-state when the chip is deselected or the outputs are disabled as in the byte-wide mode (BYTE e ``0'') In the byte-wide mode DQ15 Ab1 becomes the lowest order address for data output on DQ0 -DQ7 CHIP ENABLE Activates the device's control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels If CE and RP are high but not at a CMOS high level the standby current will increase due to current flow through the CE and RP input stages RESET DEEP POWER-DOWN Provides Three-State control Puts the device in deep power-down mode Locks the boot block from program erase When RP is at logic high level and equals 4 1V maximum the boot block is locked and cannot be programmed or erased When RP e 11 4V minimum the boot block is unlocked and can be programmed or erased When RP is at a logic low level the boot block is locked the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased therefore providing data protection during power transitions When RP transitions from logic low to logic high the flash memory enters the read-array mode OUTPUT ENABLE Gates the device's outputs through the data buffers during a read cycle OE is active low WRITE ENABLE Controls writes to the Command Register and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse
DQ0 -DQ7
IO
DQ8 -DQ15
IO
CE
I
RP
I
OE WE
I I
8
28F400BL-T B 28F004BL-T B
1 5 Pin Descriptions for x8 x16 28F400BL (Continued)
Symbol BYTE Type I Name and Function BYTE ENABLE Controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16) BYTE e ``0'' enables the byte-wide mode where data is read and programmed on DQ0 -DQ7 and DQ15 Ab1 becomes the lowest order address that decodes between the upper and lower byte DQ8 -DQ14 are tri-stated during the byte-wide mode BYTE e ``1'' enables the word-wide mode where data is read and programmed on DQ0 -DQ15 PROGRAM ERASE POWER SUPPLY For erasing memory array blocks or programming data in each block Note VPP k VPPLMAX memory contents cannot be altered DEVICE POWER SUPPLY (3 3V g0 3 5V g10%) GROUND For all internal circuitry NO CONNECT Pin may be driven or left floating DON'T USE PIN Pin should not be connected to anything
VPP
VCC GND NC DU
9
28F400BL-T B 28F004BL-T B
1 6 Pin Descriptions for x8 28F004BL
Symbol A0 -A18 A9 DQ0 -DQ7 Type I I IO Name and Function ADDRESS INPUTS for memory addresses Addresses are internally latched during a write cycle ADDRESS INPUT When A9 is at 12V the signature mode is accessed During this mode A0 decodes between the manufacturer and device ID's DATA INPUTS OUTPUTS Inputs array data on the second CE and WE cycle during a program command Inputs commands to the command user interface when CE and WE are active Data is internally latched during the write and program cycles Outputs array Intelligent Identifier and status register data The data pins float to tri-state when the chip is deselected or the outputs are disabled CHIP ENABLE Activates the device's control logic input buffers decoders and sense amplifiers CE is active low CE high deselects the memory device and reduces power consumption to standby levels RESET DEEP POWER-DOWN Provides Three-State control Puts the device in deep power-down mode Locks the Boot Block from program erase When RP is at logic high level and equals 4 1V maximum the Boot Block is locked and cannot be programmed or erased When RP e 11 4V minimum the Boot Block is unlocked and can be programmed or erased When RP is at a logic low level the Boot Block is locked the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased therefore providing data protection during power transitions When RP transitions from logic low to logic high the flash memory enters the read-array mode OE WE VPP I I OUTPUT ENABLE Gates the device's outputs through the data buffers during a read cycle OE is active low WRITE ENABLE Controls writes to the Command Register and array blocks WE is active low Addresses and data are latched on the rising edge of the WE pulse PROGRAM ERASE POWER SUPPLY For erasing memory array blocks or programming data in each block Note VPP k VPPLMAX memory contents cannot be altered DEVICE POWER SUPPLY (3 3V g0 3V 5V g10%) GROUND For all internal circuitry NO CONNECT Pin may be driven or left floating DON'T USE PIN Pin should not be connected to anything
CE
I
RP
I
VCC GND NC DU
10
28F400BL-T B 28F004BL-T B
20
28F400BL PRODUCTS DESCRIPTION
290450- 1
Figure 6 28F400BL Word Byte-Wide Block Diagram 11
28F400BL-T B 28F004BL-T B
2 1 28F400BL Memory Organization
2 1 1 BLOCKING The 28F400BL uses a blocked array architecture to provide independent erasure of memory blocks A block is erased independently of other blocks in the array when an address is given within the block address range and the Erase Setup and Erase Confirm commands are written to the CUI The 28F400BL is a random read write memory only erasure is performed by block 2 1 1 1 Boot Block Operation and Data Protection The 16-Kbyte boot block provides a lock feature for secure code storage The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of power failure or other disruption during code update This lock feature ensures absolute data integrity by preventing the boot block from being written or erased when RP is not at 12V The boot block can be erased and written when RP is held at 12V for the duration of the erase or program operation This allows customers to change the boot code when necessary while providing security when needed See the Block Memory Map section for address locations of the boot block for the 28F400BL-T and 28F400BL-B 2 1 1 2 Parameter Block Operation
2 1 2 BLOCK MEMORY MAP Two versions of the 28F400BL product exist to support two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location The 28F400BL-T memory map is inverted from the 28F400BL-B memory map 2 1 2 1 28F400BL-B Memory Map The 28F400BL-B device has the 16-Kbyte boot block located from 00000H to 01FFFH to accommodate those microprocessors that boot from the bottom of the address map at 00000H In the 28F400BL-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH The second 8-Kbyte parameter block resides in memory space from 03000H to 03FFFH The 96-Kbyte main block resides in memory space from 04000H to 0FFFFH The three 128-Kbyte main block resides in memory space from 10000H to 1FFFFH 20000H to 2FFFFH and 30000H to 3FFFFH (word locations) See Figure 7
(Word Addresses) 3FFFFH
128-Kbyte MAIN BLOCK 30000H 2FFFFH 128-Kbyte MAIN BLOCK
The 28F400BL has 2 parameter blocks (8 Kbytes each) The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information The parameter blocks can also be used to store additional boot or main code The parameter blocks however do not have the hardware write protection feature that the boot block has The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked devices See the Block Memory Map section for address locations of the parameter blocks for the 28F400BL-T and 28F400BL-B 2 1 1 3 Main Block Operation Four main blocks of memory exist on the 28F400BL (3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks) See the following section on Block Memory Map for the address location of these blocks for the 28F400BL-T and 28F400BL-B products
20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 96-Kbyte MAIN BLOCK 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK 00000H
Figure 7 28F400BL-B Memory Map
12
28F400BL-T B 28F004BL-T B
2 1 2 2 28F400BL-T Memory Map The 28F400BL-T device has the 16-Kbyte boot block located from 3E000H to 3FFFFH to accommodate those microprocessors that boot from the top of the address map In the 28F400BX-T the first 8-Kbyte parameter block resides in memory space from 3D000H to 3DFFFH The second 8-Kbyte parameter block resides in memory space from 3C000H to 3CFFFH The 96-Kbyte main block resides in memory space from 30000H to 3BFFFH The three 128-Kbyte main blocks reside in memory space from 20000H to 2FFFFH 10000H to 1FFFFH and 00000H to 0FFFFH as shown in Figure 8
(Word Addresses) 3FFFFH 16-Kbyte BOOT BLOCK 3E000H 3DFFFH 3D000H 3CFFFH 3C000H 3BFFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK 30000H 2FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 128-Kbyte MAIN BLOCK
00000H
Figure 8 28F400BL-T Memory Map
13
28F400BL-T B 28F004BL-T B
30
28F004BL PRODUCTS DESCRIPTION
290450- 3
Figure 9 28F004BL and Byte-Wide Block Diagram 14
28F400BL-T B 28F004BL-T B
3 1 28F004BL Memory Organization
3 1 1 BLOCKING The 28F004BL uses a blocked array architecture to provide independent erasure of memory blocks A block is erased independently of other blocks in the array when an address is given within the block address range and the Erase Setup and Erase Confirm commands are written to the CUl The 28F004BL is a random read write memory only erasure is performed by block 3 1 1 1 Boot Block Operation and Data Protection The 16-Kbyte boot block provides a lock feature for secure code storage The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of power failure or other disruption during code update This lock feature ensures absolute data integrity by preventing the boot block from being programmed or erased when RP is not at 12V The boot block can be erased and programmed when RP is held at 12V for the duration of the erase or program operation This allows customers to change the boot code when necessary while still providing security when needed See the Block Memory Map section for address locations of the boot block for the 28F004BL-T and 28F004BL-B 3 1 1 2 Parameter Block Operation The 28F004BL has 2 parameter blocks (8 Kbytes each) The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information The parameter blocks can also be used to store additional boot or main code The parameter blocks however do not have the hardware write protection feature that the boot block has Parameter blocks provide for more efficient memory utilization when dealing with small parameter changes versus regularly blocked devices See the Block Memory Map section for address locations of the parameter blocks for the 28F004BL-T and 28F004BL-B 3 1 1 3 Main Block Operation
3 1 2 BLOCK MEMORY MAP Two versions of the 28F004BL product exist to support two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location The 28F004BL-T memory map is inverted from the 28F004BL-B memory map 3 1 2 1 28F004BL-B Memory Map The 28F004BL-B device has the 16-Kbyte boot block located from 00000H to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at 00000H In the 28F004BL-B the first 8-Kbyte parameter block resides in memory from 04000H to 05FFFH The second 8-Kbyte parameter block resides in memory space from 06000H to 07FFFH The 96-Kbyte main block resides in memory space from 08000H to 1FFFFH The three 128-Kbyte main blocks reside in memory space from 20000H to 3FFFFH 40000H to 5FFFFH and 60000H to 7FFFH See Figure 10
7FFFFH
128-Kbyte MAIN BLOCK 60000H 5FFFFH 128-Kbyte MAIN BLOCK 40000H 3FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 96-Kbyte MAIN BLOCK 08000H 07FFFH 06000H 05FFFH 04000H 03FFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK 00000H
Two main blocks of memory exist on the 28F004BL (3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks) See the following section on Block Memory Map for the address location of these blocks for the 28F004BL-T and 28F004BL-B
Figure 10 28F004BL-B Memory Map
15
28F400BL-T B 28F004BL-T B
3 1 2 2 28F004BL-T Memory Map The 28F004BL-T device has the 16-Kbyte boot block located from 7C000H to 7FFFFH to accommodate those microprocessors that boot from the top of the address map In the 28F004BL-T the first 8-Kbyte parameter block resides in memory space from 7A000H to 7BFFFH The second 8-Kbyte parameter block resides in memory space from 78000H to 79FFFH The 96-Kbyte main block resides in memory space from 60000H to 77FFFH The three 128-Kbyte main blocks reside in memory space from 40000H to 5FFFFH 20000H to 3FFFFH and 00000H to 1FFFFH
40
PRODUCT FAMILY PRINCIPLES OF OPERATION
Flash memory augments EPROM functionality with in-circuit electrical write and erase The 4-Mbit flash memory family utilizes a Command User Interface (CUI) and internally generated and timed algorithms to simplify write and erase operations The CUI allows for fixed power supplies during erasure and programming and maximum EPROM compatibility In the absence of high voltage on the VPP pin the 4-Mbit flash family will only successfully execute the following commands Read Array Read Status Register Clear Status Register and Intelligent Identifier mode The device provides standard EPROM read standby and output disable operations Manufacturer Identification and Device Identification data can be accessed through the CUI or through the standard EPROM A9 high voltage access (VID) (for PROM programmer equipment) The same EPROM read standby and output disable functions are available when high voltage is applied to the VPP pin In addition high voltage on VPP allows write and erase of the device All functions associated with altering memory contents write and erase Intelligent Identifier read and Read Status are accessed via the CUI The purpose of the Write State Machine (WSM) is to completely automate the write and erasure of the device The WSM will begin operation upon receipt of a signal from the CUI and will report status back through a Status Register The CUI will handle the WE interface to the data and address latches as well as system software requests for status while the WSM is in operation
7FFFFH 16-Kbyte BOOT BLOCK 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK 60000H 5FFFFH 128-Kbyte MAIN BLOCK 40000H 3FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK
00000H
4 1 28F400BL Bus Operations
Flash memory reads erases and writes in-system via the local CPU All bus cycles to or from the flash memory conform to standard microprocessor bus cycles
Figure 11 28F004BL-T Memory Map
16
28F400BL-T B 28F004BL-T B
Table 1 Bus Operations for WORD-WIDE Mode (BYTE Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write 9 34 3 4 5 10 678 Notes 12 RP VIH VIH VIH VIL VIH VIH VIH CE VIL VIL VIH X VIL VIL VIL OE VIL VIH X X VIL VIL VIH WE VIH VIH X X VIH VIH VIL
e VIH)
A9 X X X X VID VID X
A0 X X X X VIL VIH X
VPP X X X X X X X
DQ0-15 DOUT High Z High Z High Z 0089H 4470H 4471H DIN
Table 2 Bus Operations for BYTE-WIDE Mode (BYTE Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write 34 3 4 5 10 678 Notes 12 RP VIH VIH VIH VIL VIH VIH VIH CE VIL VIL VIH X VIL VIL VIL OE VIL VIH X X VIL VIL VIH WE VIH VIH X X VIH VIH VIL A9 X X X X VID VID X A0 X X X X VIL VIH X
e VIL)
A-1 X X X X X X X
VPP X X X X X X X
DQ0-7 DOUT High Z High Z High Z 89H 70H 71H DIN
DQ8-14 High Z High Z High Z High Z High Z High Z High Z
NOTES 1 Refer to DC Characteristics 2 X can be VIL or VIH for control pins and addresses VPPL or VPPH for VPP 3 See DC Characteristics for VPPL VPPH VHH VID voltages 4 Manufacturer and Device codes may also be accessed via a CUI write sequence A1 -A17 e VIL 5 Device ID e 4470H for 28F400BL-T and 4471H for 28F400BL-B 6 Refer to Table 4 for valid DIN during a write operation 7 Command writes for Block Erase or Word Byte Write are only executed when VPP e VPPH 8 To write or erase the boot block hold RP at VHH 9 RP must be at GND g0 2V to meet the 1 2 mA maximum deep power-down current 10 The device ID codes are identical to those of the 28F400BX 5V version and SmartVoltage equivalent
17
28F400BL-T B 28F004BL-T B
4 2 28F004BL Bus Operations
Table 3 Bus Operations Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write 9 34 3 4 5 10 678 Notes 12 RP VIH VIH VIH VIL VIH VIH VIH CE VIL VIL VIH X VIL VIL VIL OE VIL VIH X X VIL VIL VIH WE VIH VIH X X VIH VIH VIL A9 X X X X VID VID X A0 X X X X VIL VIH X VPP X X X X X X X DQ0-7 DOUT High Z High Z High Z 89H 78H 79H DIN
NOTES 1 Refer to DC Characteristics 2 X can be VIL or VIH for control pins and addresses VPPL or VPPH for VPP 3 See DC Characteristics for VPPL VPPH VHH VID voltages 4 Manufacturer and Device codes may also be accessed via a CUI write sequence A1 -A8 A10 -A18 e VIL 5 Device ID e 78H for 28F004BL-T and 79H for 28F004BL-B 6 Refer to Table 4 for valid DIN during a write operation 7 Command writes for Block erase or byte program are only executed when VPP e VPPH 8 Program or erase the Boot block by holding RP at VHH 9 RP must be at GND g0 2V to meet the 1 2 mA maximum deep power-down current 10 The device ID codes are identical to those of the 28F004BX 5V version and SmartVoltage equivalent
4 3 Read Operations
The 4-Mbit flash family has three user read modes Array Intelligent Identifier and Status Register Status Register read mode will be discussed in detail in the ``Write Operations'' section During power-up conditions (VCC supply ramping) it takes a maximum of 600 ns from VCC at 3 0V minimum to obtain valid data on the outputs 4 3 1 READ ARRAY If the memory is not in the Read Array mode it is necessary to write the appropriate read mode command to the CUI The 4-Mbit flash family has three control functions all of which must be logically active to obtain data at the outputs Chip-Enable CE is the device selection control Power-Down RP is the device power control Output-Enable OE is the DATA INPUT OUTPUT (DQ 0 15 or DQ 0 7 ) direction control and when active is used to drive data from the selected memory onto the I O bus 4 3 1 1 Output Control With OE at logic-high level (VIH) the output from the device is disabled and data input output pins (DQ 0 15 or DQ 0 7 are tri-stated Data input is then controlled by WE
4 3 1 2 Input Control With WE at logic-high level (VIH) input to the device is disabled Data Input Output pins (DQ 0 15 or DQ 0 7 ) are controlled by OE 4 3 2 INTELLIGENT IDENTlFlERS 28F400BL PRODUCTS The manufacturer and device codes are read via the CUI or by taking the A9 pin to 12V Writing 90H to the CUI places the device into Intelligent Identifier read mode A read of location 00000H outputs the manufacturer's identification code 0089H and location 00001H outputs the device code 4470H for 28F400BL-T 4471H for 28F4001BL-B When BYTE is at a logic low only the lower byte of the above signatures is read and DQ15 Ab1 is a ``don't care'' during Intelligent Identifier mode A read array command must be written to the CUI to return to the read array mode
18
28F400BL-T B 28F004BL-T B
28F004BL PRODUCTS The manufacturer and device codes are also read via the CUI or by taking the A9 pin to 12V Writing 90H to the CUI places the device into Intelligent Identifier read mode A read of location 00000H outputs the manufacturer's identification code 89H and location 00001H outputs the device code 78H for 28F004BL-T 79H for 28F004BL-B
4 4 1 BOOT BLOCK WRITE OPERATIONS In the case of Boot Block modifications (write and erase) RP is set to VHH e 12V typically in addition to VPP at high voltage However if RP is not at VHH when a program or erase operation of the boot block is attempted the corresponding status register bit (Bit 4 for Program and Bit 5 for Erase refer to Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation 4 4 2 COMMAND USER INTERFACE (CUI) The Command User Interface (CUI) serves as the interface to the microprocessor The CUI points the read write path to the appropriate circuit block as described in the previous section After the WSM has completed its task it will set the WSM Status bit to a ``1'' which will also allow the CUI to respond to its full command set Note that after the WSM has returned control to the CUI the CUI will remain in its current state 4 4 2 1 Command Set Command Codes 00 10 20 40 50 70 90 B0 D0 FF Device Mode Invalid Reserved Alternate Program Setup Erase Setup Program Setup Clear Status Register Read Status Register Intelligent Identifier Erase Suspend Erase Resume Erase Confirm Read Array
4 4 Write Operations
Commands are written to the CUI using standard microprocessor write timings The CUI serves as the interface between the microprocessor and the internal chip operation The CUI can decipher Read Array Read Intelligent Identifier Read Status Register Clear Status Register Erase and Program commands In the event of a read command the CUI simply points the read path at either the array the Intelligent Identifier or the status register depending on the specific read command given For a program or erase cycle the CUI informs the write state machine that a write or erase has been requested During a program cycle the Write State Machine will control the program sequences and the CUI will only respond to status reads During an erase cycle the CUI will respond to status reads and erase suspend After the Write State Machine has completed its task it will allow the CUI to respond to its full command set The CUI will stay in the current command state until the microprocessor issues another command The CUI will successfully initiate an erase or write operation only when VPP is within its voltage range Depending upon the application the system designer may choose to make the VPP power supply switchable available only when memory updates are desired The system designer can also choose to ``hard-wire'' VPP to 12V The 4-Mbit flash memory family is designed to accommodate either design practice It is recommended that RP be tied to logical Reset for data protection during unstable CPU reset function as described in the ``Product Family Overview'' section
4 4 2 2 Command Function Descriptions Device operations are selected by writing specific commands into the CUI Table 4 below defines the 4-Mbit flash memory family commands
19
28F400BL-T B 28F004BL-T B
Table 4 Command Definitions Command Read Array Intelligent Identifier Read Status Register Clear Status Register Erase Setup Erase Confirm Word Byte Write Setup Write Erase Suspend Erase Resume Alternate Word Byte Write Setup Write Bus Notes First Bus Cycle Second Bus Cycle Cycles Req'd 8 Operation Address Data Operation Address Data 1 3 2 1 2 2 2 2 WD 5 67 1 24 3 Write Write Write Write Write Write Write 237 X X X X BA WA X Write FFH 90H 70H 50H 20H 40H B0H WA Write Write Write 10H BA WA X Write D0H WD D0H WA Read Read IA X IID SRD
NOTES 1 Bus operations are defined in Tables 1 2 3 2 IA e Identifier Address 00H for manufacturer code 01H for device code 3 SRD e Data read from Status Register 4 IID e Intelligent Identifier Data Following the Intelligent Identifier command two read operations access manufacturer and device codes 5 BA e Address within the block being erased 6 WA e Address to be written WD e Data to be written at location WA 7 Either 40H or 10H commands is valid 8 When writing commands to the device the upper data bus DQ8 -DQ15 e X (28F400BL-only) which is either VCC or VSS to avoid burning additional current
Invalid Reserved These are unassigned commands It is not recommended that the customer use any command other than the valid commands specified above Intel reserves the right to redefine these codes for future functions Read Array (FFH) This single write command points the read path at the array If the host CPU performs a CE OE controlled read immediately following a two-write sequence that started the WSM then the device will output status register contents If the Read Array command is given after Erase Setup the device is reset to read the array A two Read Array command sequence (FFH) is required to reset to Read Array after Program Setup Intelligent Identifier (90H) After this command is executed the CUI points the output path to the Intelligent Identifier circuits Only Intelligent Identifier values at addresses 0 and 1 can be read (only address A0 is used in this mode alI other address inputs are ignored) 20
Read Status Register (70H) This is one of the two commands that is executable while the state machine is operating After this command is written a read of the device will output the contents of the status register regardless of the address presented to the device The device automatically enters this mode after program or erase has completed Clear Status Register (50H) The WSM can only set the Program Status and Erase Status bits in the status register it can not clear them Two reasons exist for operating the status register in this fashion The first is a synchronization The WSM does not know when the host CPU has read the status register therefore it would not know when to clear the status bits Secondly if the CPU is programming a string of bytes it may be more efficient to query the status register after programming the string Thus if any errors exist while programming the string the status register wiII return the accumulated error status
28F400BL-T B 28F004BL-T B
tinue to run idling in the SUSPEND state regardless of the state of alI input control pins with the excluRP low will immediately shut down sion of RP the WSM and the remainder of the chip Erase Resume (D0H) This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a ``0'' but only if an Erase Suspend command was previously issued Erase Resume will not have any effect in all other conditions 4 4 3 STATUS REGISTER The 4 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete and whether that operation completed successfully The status register may be read at any time by writing the Read Status command to the CUI After writing this command all subsequent Read operations output data from the status register until another command is written to the CUI A Read Array command must be written to the CUl to return to the Read Array mode The status register bits are output on DQ 0 7 whether the device is in the byte-wide (x8) or wordwide (x16) mode for the 28F400BL In the word-wide mode the upper byte DQ 8 15 is set to 00H during a Read Status command In the byte-wide mode DO 8 14 is tri-stated and DQ15 Ab1 retains the low order address function It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs last in the read cycle This prevents possible bus errors which might occur if the contents of the status register change while reading the status register CE or OE must be toggled with each subsequent status read or the completion of a program or erase operation will not be evident The Status Register is the interface between the microprocessor and the Write State Machine (WSM) When the WSM is active this register will indicate the status of the WSM and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation The WSM sets status bits ``Three'' through ``Seven'' and clears bits ``Six'' and ``Seven'' but cannot clear status bits ``Three'' through ``Five'' These bits can only be cleared by the controlling CPU through the use of the Clear Status Register command
Program Setup (40H or 10H) This command simply sets the CUI into a state such that the next write will load the address and data registers Either 40H or 10H can be used for Program Setup Both commands are included to accommodate efforts to achieve an industry standard command code set Program The second write after the program setup command will latch addresses and data Also the CUI initiates the WSM to begin execution of the program algorithm While the WSM finishes the algorithm the device will output Status Register contents Note that the WSM cannot be suspended during programming Erase Setup (20H) Prepares the CUI for the Erase Confirm command No other action is taken If the next command is not an Erase Confirm command then the CUI will set both the Program Status and Erase Status bits of the Status Register to a ``1'' place the device into the Read Status Register state and wait for another command Erase Confirm (D0H) If the previous command was an Erase Setup command then the CUI will enable the WSM to erase at the same time closing the address and data latches and respond only to the Read Status Register and Erase Suspend commands While the WSM is executing the device will output Status Register data when OE is toggled low Status Register data can only be updated by toggling either OE or CE low Erase Suspend (B0H) This command only has meaning while the WSM is executing an Erase operation and therefore will only be responded to during an erase operation After this command has been executed the CUI will initiate the WSM to suspend Erase operations and then return to responding to only Read Status Register or to the Erase Resume commands Once the WSM has reached the Suspend state it will set an output into the CUI which allows the CUI to respond to the Read Array Read Status Register and Erase Resume commands In this mode the CUI will not respond to any other commands The WSM will also set the WSM Status bit to a ``1'' The WSM will con-
21
28F400BL-T B 28F004BL-T B
4 4 3 1 Status Register Bit Definition Table 5 Status Register Definitions
WSMS 7
ESS 6
ES 5
PS 4
VPPS 3
R 2
R 1
R 0
NOTES SR 7 e WRITE STATE MACHINE STATUS 1 e Ready 0 e Busy SR 6 e ERASE SUSPEND STATUS 1 e Erase Suspended 0 e Erase in Progress Completed SR 5 e ERASE STATUS 1 e Error in Block Erasure 0 e Successful Block Erase SR 4 1 0 SR 3 1 0
e e e e e e
Write State Machine Status bit must first be checked to determine byte word program or block erase completion before the Program or Erase Status bits are checked for success When Erase Suspend is issued WSM halts execution and sets both WSMS and ESS bits to ``1'' ESS bit remains set to ``1'' until an Erase Resume command is issued When this bit is set to ``1'' WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify When this bit is set to ``1'' WSM has attempted but failed to Program a byte or word The VPP Status bit unlike an A D converter does not provide continuous indication of VPP level The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if VPP has not been switched on The VPP Status bit is not guaranteed to report accurate feedback between VPPL and VPPH
PROGRAM STATUS Error in Byte Word Program Successful Byte Word Program VPP STATUS VPP Low Detect Operation Abort VPP OK
SR 2 - SR 0 e RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the Status Register
4 4 3 2 Clearing the Status Register Certain bits in the status register are set by the write state machine and can only be reset by the system software These bits can indicate various failure conditions By allowing the system software to control the resetting of these bits several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence) The status register may then be read to determine if an error occurred during that programming or erasure series This adds flexibility to the way the device may be programmed or erased To clear the status register the Clear Status Register command is written to the CUI Then any other command may be issued to the CUI Note again that before a read cycle can be initiated a Read command must be written to the CUI to specify whether the read data is to come from the array status register or Intelligent Identifier
4 4 4 PROGRAM MODE Program is executed by a two-write sequence The Program Setup command is written to the CUI followed by a second write which specifies the address and data to be programmed The write state machine will execute a sequence of internally timed events to 1 program the desired bits of the addressed memory word (byte) and 2 verify that the desired bits are sufficiently programmed Programming of the memory results in specific bits within a byte or word being changed to a ``0'' If the user attempts to program ``1''s there will be no change of the memory cell content and no error occurs
22
28F400BL-T B 28F004BL-T B
Similar to erasure the status register indicates whether programming is complete While the program sequence is executing bit 7 of the status register is a ``0'' The status register can be polled by toggling either CE or OE to determine when the program sequence is complete Only the Read Status Register command is valid while programming is active When programming is complete the status bits which indicate whether the program operation was successful should be checked If the programming operation was unsuccessful Bit 4 of the status register is set to a ``1'' to indicate a Program Failure If Bit 3 is set then VPP was not within acceptable limits and the WSM will not execute the programming sequence The status register should be cleared before attempting the next operation Any CUI instruction can follow after programming is completed however it must be recognized that reads from the memory status register or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate command A Read Array command must first be given before memory contents can be read Figure 12 shows a system software flowchart for device byte programming operation Figure 13 shows a similar flowchart for device word programming operation (28F400BL-only) 4 4 5 ERASE MODE Erasure of a single block is initiated by writing the Erase Setup and Erase Confirm commands to the CUI along with the addresses A 12 17 for the 28F400BL or A 12 18 for the 28F004BL identifying the block to be erased These addresses are latched internally when the Erase Confirm command is issued Block erasure results in all bits within the block being set to ``1'' The WSM will execute a sequence of internally timed events to 1 program all bits within the block 2 verify that all bits within the block are sufficiently programmed 3 erase all bits within the block and 4 verify that all bits within the block are sufficiently erased While the erase sequence is executing Bit 7 of the status register is a ``0'' When the status register indicates that erasure is complete the status bits which indicate whether the erase operation was successful should be checked If the erasure operation was unsuccessful Bit 5 of the status register is set to a ``1'' to indicate an Erase Failure If VPP was not within acceptable limits after the Erase Confirm command is issued the WSM will not execute an erase sequence instead Bit 5 of the status register is set to a ``1'' to indicate an Erase Failure and Bit 3 is set to a ``1'' to identify that VPP supply voltage was not within acceptable limits The status register should be cleared before attempting the next operation Any CUI instruction can follow after erasure is completed however it must be recognized that reads from the memory array status register or Intelligent Identifier can not be accomplished until the CUI is given the appropriate command A Read Array command must first be given before memory contents can be read Figure 13 shows a system software flowchart for Block Erase operation 4 4 5 1 Suspending and Resuming Erase Since an erase operation typically requires 2 seconds to 5 seconds to complete an Erase Suspend command is provided This allows erase-sequence interruption in order to read data from another block of the memory Once the erase sequence is started writing the Erase Suspend command to the CUI requests that the Write State Machine (WSM) pause the erase sequence at a predetermined point in the erase algorithm The status register must be read to determine when the erase operation has been suspended At this point a Read Array command can be written to the CUI in order to read data from blocks other than that which is being suspended The only other valid command at this time is the Erase Resume command or Read Status Register operation Figure 14 shows a system software flowchart detailing the operation During Erase Suspend mode the chip can go into a pseudo-standby mode by taking CE to VIH and the active current is now a maximum of 6 mA If the chip is enabled while in this mode by taking CE to VIL the Erase Resume command can be issued to resume the erase operation
23
28F400BL-T B 28F004BL-T B
Upon completion of reads from any block other than the block being erased the Erase Resume command must be issued When the Erase Resume command is given the WSM will continue with the erase sequence and complete erasing the block As with the end of erase the status register must be read cleared and the next instruction issued in order to continue
4 4 6 EXTENDED CYCLING Intel has designed extended cycling capability into its ETOX III flash memory technology The 4-Mbit low voltage flash memory family is designed for 10 000 program erase cycles on each of the seven blocks The combination of low electric fields clean oxide processing and minimized oxide area per memory cell subjected to the tunneling electric field results in very high cycling capability
24
28F400BL-T B 28F004BL-T B
Bus Operation Write
Command
Comments
Setup Program
Data e 40H Address e Byte to be programmed Data to be programmed Address e Byte to be programmed
Write
Program
Read
Status Register Data Toggle OE or CE to update Status Register
Standby
Check SR 7 1 e Ready 0 e Busy
Repeat for subsequent bytes Full status check can be done after each byte or after a sequence of bytes
Write FFH after the last byte programming operation to reset the device to Read Array Mode
290450 - 9
Full Status Check Procedure
Bus Operation Standby Command Comments
Check SR 3 1 e VPP Low Detect
Standby
Check SR 4 1 e Byte Program Error
SR 3 MUST be cleared if set during a program attempt before further attempts are allowed by the Write State Machine SR 4 is only cleared by the Clear Status Register Command in cases where multiple bytes are programmed before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
290450 - 10
Figure 12 Automated Byte Programming Flowchart
25
28F400BL-T B 28F004BL-T B
Bus Operation Write
Command
Comments
Setup Program
Data e 40H Address e Word to be programmed Data to be programmed Address e Word to be programmed
Write
Program
Read
Status Register Data Toggle OE or CE to update Status Register
Standby
Check SR 7 1 e Ready 0 e Busy
Repeat for subsequent words Full status check can be done after each word or after a sequence of words
290450 - 11
Write FFH after the last word programming operation to reset the device to Read Array Mode
Full Status Check Procedure
Bus Operation Standby Command Comments
Check SR 3 1 e VPP Low Detect
Standby
Check SR 4 1 e Byte Program Error
SR 3 MUST be cleared if set during a program attempt before further attempts are allowed by the Write State Machine SR 4 is only cleared by the Clear Status Register Command in cases where multiple words are programmed before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
290450 - 12
Figure 13 Automated Word Programming Flowchart
26
28F400BL-T B 28F004BL-T B
Bus Operation Write
Command
Comments
Setup Erase
Data e 20H Address e Within block to be erased Data e D0H Address e Within block to be erased
Write
Erase
Read
Status Register Data Toggle OE or CE to update Status Register
Standby
Check SR 7 1 e Ready 0 e Busy
Repeat for subsequent blocks Full status check can be done after each block or after a sequence of blocks
290450 - 13
Write FFH after the last block erase operation to reset the device to Read Array Mode
Full Status Check Procedure
Bus Operation Standby
Command
Comments
Check SR 3 1 e VPP Low Detect
Standby
Check SR 4 5 Both 1 e Command Sequence Error Check SR 5 1 e Block Erase Error
Standby
SR 3 MUST be cleared if set during an erase attempt before further attempts are allowed by the Write State Machine
290450 - 14
SR 5 is only cleared by the Clear Status Register Command in cases where multiple blocks are erased before full status is checked If error is detected clear the Status Register before attempting retry or other error recovery
Figure 14 Automated Block Erase Flowchart 27
28F400BL-T B 28F004BL-T B
Bus Operation
Command
Comments
Write
Erase Suspend
Data e B0H
Read
Status Register Data Toggle OE or CE to update Status Register
Standby
Check SR 7 1 e Ready
Standby
Check SR 6 1 e Suspended
Write
Read Array
Data e FFH
Read
Read array data from block other than that being erased
Write
290450 - 15
Erase Resume
Data e D0H
Figure 15 Erase Suspend Resume Flowchart
4 5 Power Consumption
4 5 1 ACTIVE POWER With CE at a logic-low level and RP at a logichigh level the device is placed in the active mode The device ICC current is a maximum of 22 mA at 5 MHz 4 5 2 AUTOMATIC POWER SAVINGS Automatic Power Savings (APS) is a low power feature during active mode of operation The 4-Mbit family of products incorporate Power Reduction Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is not being accessed After data is read from the memory array PRC logic controls the device's power consumption by entering the APS mode where
typical ICC current is 0 8 mA and maximum ICC current is 2 mA The device stays in this static state with outputs valid until a new memory location is read 4 5 3 STANDBY POWER With CE at a logic-high level (VIH) and the CUI read mode the memory is placed in standby mode where the maximum ICC standby current is 120 mA with CMOS input signals The standby operation disables much of the device's circuitry and substantially reduces device power consumption The outputs (DQ 0 15 or DQ 0 7 are placed in a high-impedance state independent of the status of the OE signal When the 4-Mbit flash family is deselected during erase or program functions the devices will continue to perform the erase or program function and consume program or erase active power until program or erase is completed
28
28F400BL-T B 28F004BL-T B
active Since both WE and CE must be low for a command write driving either signal to VIH will inhibit writes to the device The CUl architecture provides an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences Finally the device is disabled until RP is brought to VIH regardless of the state of its control inputs This feature provides yet another level of memory protection
4 5 4 RESET DEEP POWER-DOWN The 4-Mbit flash family supports a typical ICC of 0 2 mA in deep power-down mode One of the target markets for these devices is in portable equipment where the power consumption of the machine is of prime importance The 4-Mbit flash family has a RP pin which places the device in the deep powerdown mode When RP is at a logic-low (GND g0 2V) all circuits are turned off and the device typically draws 0 2 mA of VCC current During read modes the RP pin going low deselects the memory and places the output drivers in a high impedance state Recovery from the deep power-down state requires a maximum of 600 ns to access valid data (tPHQV) During erase or program modes RP low will abort either erase or program operation The contents of the memory are no longer valid as the data has been corrupted by the RP function As in the read mode above all internal circuitry is turned off to achieve the 0 2 mA current level RP transitions to VIL or turning power off to the device will clear the status register This use of RP during system reset is important with automated write erase devices When the system comes out of reset it expects to read from the flash memory Automated flash memories provide status information when accessed during write erase modes If a CPU reset occurs with no flash memory reset proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data Intel's Flash Memories allow proper CPU initialization following a system reset through the use of the RP input In this application RP is controlled by the same RESET signal that resets the system CPU
4 7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods System designers are interested in 3 supply current issues
Standby current levels (ICCS) Active current levels (ICCR) Transient peaks produced by falling and rising
edges of CE Transient current magnitudes depend on the device outputs' capacitive and inductive loading Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks Each flash device should have a 0 1 mF ceramic capacitor connected between each VCC and GND and between its VPP and GND These high frequency lowinherent inductance capacitors should be placed as close as possible to the package leads 4 7 1 VPP TRACE ON PRINTED CIRCUIT BOARDS Writing to flash memories while they reside in the target system requires special consideration of the VPP power supply trace by the printed circuit board designer The VPP pin supplies the flash memory cell's current for programming and erasing One should use similar trace widths and layout considerations given to the VCC power supply trace Adequate VPP supply traces and decoupling will decrease spikes and overshoots 4 7 2 VCC VPP AND RP TRANSITIONS
4 6 Power-up Operation
The 4-Mbit flash memory family is designed to offer protection against accidental block erasure or programming during power transitions Upon power-up the 4-Mbit flash memory family is indifferent as to which power supply VPP or VCC powers-up first Power supply sequencing is not required The 4-Mbit flash memory family ensures the CUI is reset to the read mode on power-up In addition on power-up the user must either drop CE low or present a new address to ensure valid data at the outputs A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is
The CUI latches commands as issued by system software and is not altered by VPP or CE transitions or WSM actions Its state upon power-up after exit from deep power-down mode or after VCC transitions below VLKO (Lockout voltage) is Read Array mode After any word byte write or block erase operation is complete and even after VPP transitions down to VPPL the CUI must be reset to Read Array mode via the Read Array command when accesses to the flash memory are desired 29
28F400BL-T B 28F004BL-T B
5 0 OPERATING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS
Operating Temperature b 20 C to a 70 C(1) During Read During Block Erase Byte Write 0 C to a 70 C b 20 C to a 80 C Temperature Under Bias Storage Temperature
b 65 C to a 125 C
NOTICE This is a production data sheet The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
Voltage on any Pin (except VCC VPP A9 and RP ) b 2 0V to a 7 0V(2) with Respect to GND Voltage on Pin RP or Pin A9 b 2 0V to a 13 5V(2 3) with Respect to GND VCC Program Voltage with Respect to GND during Block Erase and b 2 0V to a 14 0V(2 3) Word Byte Write VCC Supply Voltage with Respect to GND Output Short Circuit Current
b 2 0V to a 7 0V(2)
100 mA(4)
OPERATING CONDITIONS
Symbol TA VCC VCC Parameter Operating Temperature VCC Supply Voltage VCC Supply Voltage Program Erase Read 5 Notes Min
b 20
Max 70 3 60 3 60 5 50
Unit C V V V
3 15 3 00 4 50
NOTES 1 Operating temperature is for commercial product defined by this specification 2 Minimum DC voltage is b0 5V on input output pins During transitions this level may undershoot to b2 0V for periods k 20 ns Maximum DC voltage on input output pins is VCC a 0 5V which during transitions may overshoot to VCC a 2 0V for periods k 20 ns 3 Maximum DC voltage on VPP may overshoot to a 14 0V for periods k20 ns Maximum DC voltage on RP or A9 may overshoot to 13 5V for periods k 20 ns 4 Output shorted for no more than one second No more than one output shorted at a time 5 AC specifications are valid at both voltage ranges See DC Characteristics tables for voltage range-specific specifications
DC CHARACTERISTICS
VCC e 3 3V g0 3V Read 3 15V-3 6V Program Erase Symbol ILI ILO Parameter Input Load Current Output Leakage Current Notes 1 1 Min Typ Max
g1 0
Unit mA mA
Test Conditions VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND
g10
30
28F400BL-T B 28F004BL-T B
DC CHARACTERISTICS (Continued)
VCC e 3 3V g0 3V Read 3 15V-3 6V Program Erase Symbol ICCS Parameter VCC Standby Current Notes Min Typ 13 45 45 Max 120 120 Unit Test Conditions
mA VCC e VCC Max CE e RP e VIH mA VCC e VCC Max CE e RP e VCC g0 2V 28F400BX BYTE e VCC g0 2V or GND mA RP
e GND g0 2V
ICCD ICCR
VCC Deep Power-Down Current VCC Read Current for 28F400BX-L Word-Wide and Byte-Wide Mode and 28F004BX-L Byte-Wide Mode
1 1 56
0 20 15
12 25
mA VCC e VCC Max CE e GND f e 5 MHz IOUT e 0 mA CMOS Inputs mA VCC e VCC Max CE e VIL f e 5 MHz IOUT e 0 mA TTL Inputs mA Word Write in Progress mA Byte Write in Progress mA Block Erase in Progress mA CE e VIH Block Erase Suspended mA VPP s VCC mA RP
e GND g0 2V
15
25
ICCW ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPW IPPE IPPES IRP IID VID VIL VIH VOL
VCC Word Write Current VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Read Current VPP Word Write Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current RP Boot Block Unlock Current
1 1 1 12 1 1 14 14 14 14 1 14 14 11 4 12 0
b0 5
30 30 20 3 6
g15
50 200 40 30 30 200 500 500 13 0 06 VCC a 0 5 04
mA VPP l VCC mA VPP e VPPH Word Write in Progress mA VPP e VPPH Byte Write in Progress mA VPP e VPPH Block Erase in Progress mA VPP e VPPH Block Erase Suspended mA RP
e VHH
A9 Intelligent Identifier Current A9 Intelligent Identifier Voltage Input Low Voltage Input High Voltage Output Low Voltage
mA A9 e VID V V V V VCC e VCC Min IOL e 2 mA
20
31
28F400BL-T B 28F004BL-T B
DC CHARACTERISTICS (Continued)
VCC e 3 3V g0 3V Read 3 15V-3 6V Program Erase Symbol VOH1 VOH2 Parameter Output High Voltage (TTL) Output High Voltage (CMOS) Notes Min 24 0 85 VCC VCC b 0 4 VPPL VPPH VLKO VHH VPP during Normal Operations VPP during Erase Write Operations VCC Erase Write Lock Voltage RP Unlock Voltage 3 00 11 4 20 11 4 12 0 13 0 41 12 0 12 6 V V V V Boot Block Write Erase Typ Max Unit V V Test Conditions VCC e VCC Min IOH e b 2 mA VCC e VCC Min IOH e b 2 5 mA VCC e VCC Min IOH e b 100 mA
NOTES 1 All currents are in RMS unless otherwise noted Typical values at VCC e 3 3V VPP e 12 0V T e 25 C These currents are valid for all product versions (packages and speeds) 2 ICCES is specified with the device deselected If the device is read while in Erase Suspend Mode current draw is the sum of ICCES and ICCR 3 Block Erase and Word Byte Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL 4 Sampled not 100% tested 5 Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation 6 CMOS Inputs are either VCC g0 2V or GND g0 2V TTL Inputs are either VIL or VIH
CAPACITANCE(1)
Symbol CIN COUT
TA e 25 C f e 1 MHz Parameter Typ 6 10 Max 8 12 Unit pF pF Condition VIN e 0V VOUT e 0V
Input Capacitance Output Capacitance
NOTE 1 Sampled not 100% tested
32
28F400BL-T B 28F004BL-T B
DC CHARACTERISTICS(4)
VCC e 5 0V g10% Symbol ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current Notes Min 1 1 1 Typ Max
g1 0
Unit mA mA mA mA
Test Conditions VCC e VCC Max VIN e VCC or GND VCC e VCC Max VOUT e VCC or GND VCC e VCC Max CE e RP e VIH VCC e VCC Max CE e RP e VCC g0 2V RP e GND g0 2V IOUT e 0 mA VCC e VCC Max CE e GND f e 5 MHz IOUT e 0 mA CMOS Inputs VCC e VCC Max CE e VIL f e 5 MHz IOUT e 0 mA TTL Inputs Word Write in Progress Block Erase in Progress Block Erase Suspended CE e VIH VPP s VCC RP
e GND g0 2V
g10
15 100
ICCD ICCR
VCC Deep Power-Down Current VCC Read Current for 28F400BX-L Word-Wide Mode and Byte Wide Mode and 28F004BX-L
1 1
12 40
mA mA
40
mA
ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPW IPPE IPPES IRP IID VID
VCC Word Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Read Current VPP Word Write Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current RP Boot Block Unlock Current A9 Intelligent Identifier Current A9 Intelligent Identifier Voltage
14 14 12 1 1 1 14 14 14 1 14 14 11 4 12 0
70 30 10
g10
mA mA mA mA mA mA mA mA mA mA mA mA V
50 200 40 30 30 200 500 500 13 0
VPP l VCC VPP e VPPH Word Write in Progress VPP e VPPH Byte Write in Progress VPP e VPPH Block Erase in Progress VPP e VPPH Block Erase Suspended RP
e VHH
A9 e VID
33
28F400BL-T B 28F004BL-T B
DC CHARACTERISTICS(4) (Continued)
VCC e 5 0V g10% Symbol VIL VIH VOL VOH1 VOH2 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) 24 0 85 VCC VCC b 0 4 VPPL VPPH VLKO VHH VPP during Normal Operations VPP during Erase Write Operations VCC Erase Write Lock Voltage RP Unlock Voltage 3 00 11 4 22 11 4 12 0 13 0 12 0 65 12 6 V V V V Boot Block Write Erase Notes Min
b0 5
Typ
Max 08 VCC a 0 5 0 45
Unit V V V V V
Test Condition
20
VCC e VCC Min IOL e 5 8 mA VCC e VCC Min IOH e b 2 5 mA VCC e VCC Min IOL e b 2 5 mA VCC e VCC Min IOL e b 100 mA
NOTES 1 All currents are in RMS unless otherwise noted Typical values at VCC e 5 0V VPP e 12 0V T e 25 C These currents are valid for all product versions (packages and speeds) 2 ICCES is specified with the device deselected If the device is read while in Erase Suspend Mode current draw is the sum of ICCES and ICCR 3 Block Erases and Word Byte Writes are inhibited when VPP e VPPL and not guaranteed in the range between VPPH and VPPL 4 All parameters are sampled not 100% tested
AC INPUT OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
290450 - 16
AC test inputs are driven at 3 0V for a Logic ``1'' and 0 0 for a Logic ``0'' Input timing begins and output timing ends at 1 5V Input rise and fall times (10% to 90%) k 10 ns
290450 - 17
CL e 50 pF CL Includes Jig Capacitance RL e 3 3 KX
34
28F400BL-T B 28F004BL-T B
AC CHARACTERISTICS-Read-Only Operations(1)
VCC e 3 3V g0 3V 5 0V g10% Versions Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHOZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH tIR tIF tELFL tELFH tFHQV tFLQZ Read Cycle Time Address to Output Delay CE RP OE CE CE OE OE to Output Delay High to Output Delay to Output Delay to Output Low Z High to Output High Z to Output Low Z High to Output High Z or OE 2 3 3 3 3 3 0 10 10 Switching Low or High 3 34 3 5 150 45 0 45 0 55 2 Parameter Notes 28F400BL-150 28F004BL-150 Min 150 150 150 600 65 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Output Hold from Addresses CE Change Whichever is First Input Rise Time Input Fall Time CE to BYTE
BYTE BYTE
Switching High to Valid Output Delay Switching Low to Output High Z
NOTES 1 See AC Input Output Reference Waveform for timing measurements 2 OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE 3 Sampled not 100% tested 4 tFLQV BYTE switching low to valid output delay will be equal to tAVQV measured from the time DQ15 A-1 becomes valid
35
28F400BL-T B 28F004BL-T B
Figure 16 AC Waveforms for Read Operations 36
290450- 18
28F400BL-T B 28F004BL-T B
290450 - 25
Figure 17 BYTE
Timing Diagram for Both Read and Write Operations
37
28F400BL-T B 28F004BL-T B
AC CHARACTERISTICS FOR WE -CONTROLLED WRITE OPERATIONS(1)
VCC e 3 15V-3 6V 5 0V g10% Versions(4) Symbol tAVAV tPHWL tELWL tPHHWH tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQVVL tQVPH tPHBR tIR tIF tVPH tPHH tWC tPS tCS tPHS tVPS tAS tDS tWP tDH tAH tCH tWPH Parameter Write Cycle Time RP High Recovery to WE Going Low CE Setup to WE Going Low RP VHH Setup to WE Going High VPP Setup to WE Going High 68 58 3 4 Notes 28F400BL-150 28F004BL-150 Min 150 10 0 200 200 95 100 100 High High 4 3 0 10 10 50 256 256 256 256 58 68 78 6 03 03 06 0 0 200 10 10 Max ns ms ns ns ns ns ns ns ns ns ns ns ms s s s ns ns ns ns ns Unit
Address Setup to WE Going High Data Setup to WE WE Pulse Width Going High
Data Hold from WE WE High
Address Hold from WE CE WE Hold from WE
High
Pulse Width High
Duration of Word Byte Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) VPP Hold from Valid SRD RP VHH Hold from Valid SRD Boot-Block Relock Delay Input Rise Time Input Fall Time
NOTES 1 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC Characteristics during Read Mode 2 The on-chip WSM completely automates program erase operations program erase algorithms are now controlled internally which includes verify and margining operations 3 Refer to command definition table for valid AIN 4 Refer to command definition table for valid DIN 5 Program Erase durations are measured to valid SRD data (successful operation SR 7 e 1) 6 For Boot Block Program Erase PWD should be held at VHH until operation completes successfully 7 Time tPHBR is required for successful relocking of the Boot Block 8 Sampled but not 100% tested
38
28F400BL-T B 28F004BL-T B
BLOCK ERASE AND BYTE WORD WRITE PERFORMANCE VCC e 3 15V-3 6V 5 0V g10% Parameter Boot Parameter Block Erase Time Main Block Erase Time Main Block Byte Program Time Main Block Word Program Time
NOTES 1 25 C 12 0V VPP 2 Excludes System-Level Overhead
Notes Min 2 2 2 2
28F400BL-150 28F004BL-150 Typ(1) 20 34 14 07 Max 86 17 0 53 27
Unit s s s s
39
28F400BL-T B 28F004BL-T B
Figure 18 AC Waveforms for Write and Erase Operations (WE -Controlled Writes) 40
290450- 19
28F400BL-T B 28F004BL-T B
AC CHARACTERISTICS FOR CE -CONTROLLED WRITE OPERATIONS
VCC e 3 15V-3 6V 5 0V g10% Versions Symbol tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR tIR tIF tVPH tPPH tWC tPS tWS tPHS tVPS tAS tDS tCP tDH tAH tWH tCPH Write Cycle Time RP CE WE RP High Recovery to Going Low Setup to CE Going Low Going High 68 58 3 4 Parameter Notes 28F400BL-150 28F004BL-150 Min 150 10 0 200 200 95 100 100 High High 4 3 0 10 10 50 256 256 256 256 58 68 78 6 03 03 06 0 0 200 10 10 Max ns ms ns ns ns ns ns ns ns ns ns ns ms s s s ns ns ns ns ns Unit
VHH Setup to CE
VPP Setup to CE Data Setup to CE CE Pulse Width
Going High Going High
Address Setup to CE
Going High
Data Hold from CE
Address Hold from CE WE CE Hold from CE
High
Pulse Width High
Duration of Programming Operation Word Byte Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) VPP Hold from Valid SRD RP VHH Hold from Valid SRD Boot-Block Relock Delay Input Rise Time Input Fall Time
NOTES 1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE and WE in systems where CE defines the write pulse-width (within a longer WE timing waveform) all set-up hold and inactive WE times should be measured relative to the CE waveform 2 3 4 5 6 7 8 Refer to AC Characteristics for WE -Controlled Write operations 9 Read timing characteristics during write and erase operations are the same as during read-only operations Refer to AC Characteristics during Read Mode
41
28F400BL-T B 28F004BL-T B
Figure 19 Alternate AC Waveforms for Write and Erase Operations (CE -Controlled Writes) 42
290450- 20
28F400BL-T B 28F004BL-T B
ORDERING INFORMATION
290450 - 21
VALID COMBINATIONS E28F400BL-T150 PA28F400BL-T150 E28F400BL-B150 PA28F400BL-B150
290450 - 22
VALID COMBINATIONS E28F004BL-T150 E28F004BL-B150
ADDITIONAL INFORMATION References
Order Number 290448 290449 290451 290531 290530 290539 292098 292148 292178 292130 292154 Document 28F002 200-T B Mbit Boot Block Flash Memory Datasheet 28F002 200BL-T B 2 Mbit Low Power Boot Block Flash Memory Datasheet 28F004 400BX-T B 4-Mbit Boot Block Flash Memory Datasheet 2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet AP-363 ``Extended Flash BIOS Concepts for Portable Computers'' AP-604 ``Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM'' AP-623 ``Multisite Layout Planning Using Intel's Boot Block Flash Memory'' AB-57 ``Boot Block Architecture for Safe Firmware Updates'' AB-60 ``2 4 8-Mbit SmartVoltage Boot Block Flash Memory Family''
43
28F400BL-T B 28F004BL-T B
Revision History
Number -001 -002 -003 Original Version Modified BYTE Timing Waveforms Modified tDVWH parameter for AC Characteristics for Write Operations PWD renamed to RP for JEDEC standarization compatibility Combined VCC Read Current for 28F400BX-L Word-Wide and Byte-Wide Mode and 28F004BX-L Byte Wide Mode in DC Characteristics tables Changed IPPS current spec from g10 mA to g15 mA in DC Characteristics table Added Boot Block Unlock current spec in DC Characteristics tables Improved tPWH spec to 600 ns (was 700 ns) Changed ICCR maximum spec from 20 mA to 25 mA and added 15 mA typical spec in DC Characteristics Table -004 Added IOH CMOS specification Expanded temperature operating range from 0 C-70 C to b 20 C-70 C Product naming changed 28F400BX-TL BL changed to 28F400BL-T B 28F004BX-TL BL changed to 28F004BL-T B Typographical errors corrected Added 28F400BX interface to Intel386 TM EX Embedded Processor block diagram Added upgrade considerations for SmartVoltage Boot Block products Previously specified VCC tolerance of 3 0V to 3 6V for Read Program and Erase has been changed to 3 15V to 3 6V for Program and Erase while Read remains 3 0V to 3 6V -005 Added references to input rise fall times Description
44

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